1. Field of the Invention
The present invention relates to a system using a semiconductor device for retrieving an input signal effectively synchronous with an external clock in synchronism with an internal clock generated from the external clock, and a semiconductor device used for the system, or more in particular to a semiconductor device system adapted to retrieve an input signal at a predetermined timing by adjusting the timing of the internal clock in the case where a skew exists between signals or the ambient temperature or the source voltage undergoes a fluctuation, and a semiconductor device used for the system.
2. Description of the Related Art
A large-scale semiconductor device system including a computer using a semiconductor device is configured in such a manner that each portion of the system is synchronized with a clock, and the input/output operation of signals including data signals and address signals are executed in synchronism with the clock signal. A memory operated in accordance with a clock supplied from an external source is called the synchronous type, and a DRAM (dynamic random access memory) of synchronous type is called the SDRAM. The present invention primarily relates to the SDRAM, which will be mainly referred to in the description that follows. Nevertheless, the present invention is not confined to the SDRAM.
In recent years, the increased speed of clocks for CPUs or the increased processing speed of various other electronic circuits have given rise to a demand for increasing the speed of interfaces connecting semiconductor devices. The SDRAM is a semiconductor device meeting this demand for higher speed, and continuous addresses therein can be accessed very quickly. Signals on a data bus undergo a change with a very short period, and therefore it is necessary to retrieve the signals from the data bus at high speed.
In the case where a semiconductor device retrieves an input signal, a period is defined during which the input signal is required to be established before and after the timing of retrieval. The period during which the input signal is required to be established before the retrieval timing is called a set-up time, and the period during which the input signal is required to be established after the retrieval timing is called a hold time.
With the ever increasing speed of CPU clocks in computer systems and various electronic circuits in recent years, an increased speed of the interfaces connecting semiconductor devices is urgently required. In a high-speed system using such high-speed semiconductor devices, the input establishment time for each semiconductor device to retrieve the input signal defines the system speed. The input establishment time of the semiconductor devices should therefore be reduced.
In a low-speed system, the period before a signal is established is relatively small as compared with the clock period, and poses no problem. Such a period poses a very serious problem, however, for a high-speed system with a very short clock period. For this reason, in high-speed systems measure are taken to equalize the length of the clock signal line and the lengths of other signal lines as far as possible. In spite of this, it is difficult to equalize the wiring lengths and loads exactly, and some phase difference is unavoidable, thereby posing a barrier to an increased speed.
Another problem is that of the phase difference for the semiconductor device at the receiving end. The clock input circuit has a configuration equivalent to the input circuits for other input signals, so that an arrangement is made to assure the same delay of the clock period and the input signal applied to the semiconductor device before being transmitted to a latch circuit. Actually, however, it is impossible to design the circuits to be completely identical to each other. For this reason, although the delay amounts are set as close to each other as possible, somewhat different circuits and wirings are unavoidable. Taking into consideration the variations in the production process and the temperature dependency and the source voltage dependency of the delay amount, the delay amount is differentiated even in the case where the clock input circuit is equivalent to the signal input circuit. Due to the difference in delay amount, the input establishment time required by the circuit operation varies somewhat from the rising edge of the clock CLK. The input establishment time is required to be included in the effective signal period, and in the case where this condition fails to be met, a normal input signal retrieval is impossible. Conventionally, however, the input establishment time, i.e., the set-up time and the hold time required for the circuit operation are defined taking these variations into consideration.
With the recent increase in the CPU clock speed and the processing speed of various electronic circuits in the computer systems, there is an ever increasing demand for a higher speed of the interfaces connecting the semiconductor devices. In a high-speed system using such high-speed semiconductor devices, the input establishment time for each semiconductor device to retrieve the input signal defines the system speed, and it is necessary to reduce the input establishment time of the semiconductor devices.